• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    According to an embodiment of the present invention, a word line for driving a word line connected to a plurality of memory cells having a matrix structure consisting of M rows and N columns in a semiconductor memory device by a memory address signal generated from an upper controller is generated. In particular, the driving circuit is divided into N word lines provided with n word line groups, and one-to-one matching is connected to each of the divided n word line groups, and the word line group is selected according to a control signal. Determining which of the n word line groups belongs to the n word line group driving means for activating any one of the word lines to belong, and the word line to be driven by the memory address signal generated by the upper control section. Of the n word line group driving means According to a word line driving circuit of a semiconductor memory comprising a word line selecting unit for selecting one, a word line driving block having a plurality of word lines is provided, and Pxk ( k = 0, 1, 2, 3, ..., n) Coding divides the RDPR / WLEC into n control signals to drive the RDWLD block, reducing current consumption by nearly 1 / k and reducing You can implement speed.
    公开号:KR19980056445A
    申请号:KR1019960075715
    申请日:1996-12-28
    公开日:1998-09-25
    发明作者:강창만；이창진
    申请人:문정환；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Word Line Driver Circuit in Semiconductor Memory
    1 is a word line driving circuit diagram of a semiconductor memory according to the prior art;
    FIG. 2 is a schematic block diagram of a block relationship between a word line driver circuit and a peripheral circuit to which the concept of FIG. 1 is applied. FIG.
    3 is a schematic block diagram showing the configuration between a word line driver circuit and a peripheral circuit according to the present invention.
    4 is a word line driver circuit diagram according to the present invention.
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a driving circuit of a word line connected to a memory cell by decoding a row address.
    In general, the word line driver circuit of the semiconductor memory is constructed from an X address buffer (not shown), as shown in FIG. As the input From the predecoder (PDCR) section and the X address buffer (XADB) As the input NAND gate units NAGO and NACG having an output and outputted from the predecoder PDCR Is generated from the switch transistors Q13 to Q16 that receive a signal to the gate terminal and a timing controller (TC) not shown. An X address decoder (XDCR) block for driving the transistors Q23 to Q26 and word lines that receive signals to the gate terminals The overall block of the word line driving circuit of the semiconductor memory having such a configuration is as shown in FIG.
    Referring to the overall operation of the configuration described above, the address generated in the X address buffer (XADB) to drive the word line connected to the memory cell Wow Receive high power level signal and decode to NAND type Has a signal. The signal selected in decoding has a low voltage level. At this time, the predecode (PDCR) Any one of the transistors corresponding to the reference numerals Q13, Q14, Q15, and Q16 shown in Fig. 1 is turned on by one of the high-level signals among the signals, so that the X address decoder (XDCR) (WDO, WD3, Wdm-3, The word line is driven for a certain period by turning on the transistor corresponding to the reference number Qd1 of the block Wdm).
    However, in the above structure, when applied to a memory cell block having a plurality of word lines, the required word lines have a large loading, thereby increasing the word line driver size. Therefore, in order to operate the word line driver, the block for decoding the address and the precharge transistor size also become large. As a result, as a large amount of current is consumed in each operation, power consumption increases and speed decreases.
    An object of the present invention for solving the above problems is to include a word line driving block having a plurality of word lines and to select and drive one word line, Pxk (k = 0, 1, 2, 3, ... n) By dividing the RDPR / WLEC through n control signals by coding to drive the RDWLD block, it is possible to provide a word line driving circuit that can reduce current consumption by almost 1 / K and realize high speed.
    A feature of the present invention for achieving the above object is, by a memory address signal generated from the upper control unit N word lines connected to a plurality of memory cells having a matrix structure consisting of M rows and N columns in a semiconductor memory device In a word line driving circuit for driving a corresponding word line, the N word lines provided are divided into n word line groups, and one-to-one symmetry is connected to each of the divided n word line groups and selected according to a control signal. In this case, the n word line group driving means for activating any one of the word lines belonging to the word line group, and the word line to be driven by the memory address signal generated from the upper controller side are the n word line group. To determine which of the following n corresponding wars Having drive means which comprises line groups the word lines to select one of the select portion.
    Another feature of the present invention for achieving the above object is, in a semiconductor memory device, N word lines connected to a plurality of memory cells having a matrix structure consisting of N rows and M columns are connected to a memory address signal generated at an upper controller side. In a word line driving circuit for driving a corresponding word line, an N word line is divided into n word line groups, and an address is provided from a row address buffer that stores a memory address signal generated by the upper control unit. A row address pre-decoder for receiving control signals of a predetermined form, a bit line selection circuit for generating a signal for receiving an address from the row address buffer and selecting a bit line corresponding to the address, and the n word line groups One to one for each N low decoders that receive a control signal of some of the control signals output from the low address predecoder according to an input driving control signal and drive n word line groups connected by the control signal; A word line driving circuit and a signal output from the bit line selection circuit and a low address predecoder are input to determine a word line group corresponding to a memory address signal generated from the upper controller, and accordingly the n low decoders and words And a word line selector for selecting one of the line driver circuits and inputting a driving control signal to the corresponding low decoder and the word line driver circuit.
    Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
    3 is a simplified block diagram of a word line driving circuit for driving a word line connected to a memory cell in a semiconductor memory device according to the present invention, in which a row address predecoder (XPREDEC) block receiving an address from a row address buffer is PXb, PXO, PX1, PXk (k = 0, 1, 2, 3, ..., n), PXi, PXj signals are generated and the bit line selection circuit BLS generates BEQENJB. The low fuse section (ROPTUSE) generates RDENi, RWLENI, and RWLENK signals.
    Signals PXb, PXk (k = 0, 1, 2, 3, ..., n) output from the bit line selection circuit BLS, the low fuse unit ROWFUSE and the low address predecoder XPREDEC, RDENi , Word line selection unit 200 receiving BEQENJB, PXO, PX1) is WLENOOB, WLENO1B, RPCO, RPPO, WLEN10B, WLEN11B, RPC1, RPP1, WLEN20B, WLEN21B, RPC2, RPP2, ..., WLENn0B, WLENn1B, WLENn0B The RPCn and RPPn signals are output and transferred to the n low decoders and the word line driver circuit 100.
    In this case, each of the n low decoders and the word line driver circuits 100 receives a plurality of words by inputting signals output from the word line selector 200 and output signals PXi and PXj of the low address predecoder XPRE. Raises the line.
    The detailed configuration and operation of the word line driver will be described with reference to FIG. 4 in the simplified block relationship configuration between the word line driver circuit and the peripheral circuit according to the present invention.
    4 is a block diagram of a word line driver circuit according to the present invention.
    The word line selection circuit unit 200A includes signals PXb, PXk (k = 0), RDENi, BEQENJB, PX0, which are output from the bit line selection circuit BLS and the low fuse unit ROWFUSE and the low address predecoder XPRE. PX1) is input to generate the precharge signal RPCO at the VCC voltage level, the precharge signal RPPO at the VPP voltage level, and the WLENOOB and WLENO1B signals for finally selecting the word line.
    In addition, the WLEN10B which finally selects the precharge signal RPC1 of the VCC voltage level, the precharge signal RPP1 of the VPP suppression level, and the word line by inputting the signals PXb, PXk (k = 1), RDENi, BEQENJB, PXO, and PX1. And generate the WLEN11B signal.
    In addition, WLEN20B which finally selects the precharge signal RPC2 at the VCC voltage level, the precharge signal RTP2 at the VPP voltage level, and the word line by inputting the signals PXb, PXk (k = 2), RDENi, BEQENJB, PX0, and PX1. And signal WLEN21B.
    The above-described process is repeated until k reaches n, and PXb, PXk (k = n), RDENi, BEQENJB, PX0, and PX1 signals are input as precharge signals RPCn and VPP voltage level of VCC voltage level. Generates the WLENn0B and WLENn1B signals that finally select the precharge signal RPPn and word line.
    The redundant word line selection circuit unit 200B receives PXb, PXk (k = 0, 1, 2, 3, ..., n), RWLENI, and RWLENK signals as inputs, and a precharge signal RPCr having a VCC voltage level and VPP WLENr0B and WLENr1B, which finally selects the voltage level precharge signal RPCr and word line, are generated, and further, the word line enable signals RWLEN0 and RWLEN1 are generated.
    As described above, operations of the first row decoder and the word line driver 100A receiving the data output from the word line selection circuit unit 200A for outputting various data for driving the word line are as follows.
    First, the RPCO 50, RPPO 51, Pxi, and Pxj signals input from the word line selection circuit unit 200A are connected to transistors corresponding to the reference numerals P10, N30, N31, and N32, and connected to the Pxi and PXj signals. The decoded signal is latched by an inverter corresponding to reference numeral I40 and a transistor corresponding to P11.
    The node corresponding to reference numeral 56 has a low level voltage due to the turn-on of the transistor corresponding to N33 among the switch transistors corresponding to the reference numerals N33 and N34 connected to the signals WLEN00B and WLEN01B corresponding to the reference numerals 53 and 52. The transistor corresponding to reference numeral P14 is turned on and the transistor corresponding to reference numeral N35 is turned off.
    After that, the word line WL0 of the word line Vpp level is driven for a predetermined time. When the N33 transistor is turned off and the RPP0 51 becomes a low level voltage during non-coding, the P12 transistor is operated to bring the node 56 to the VPP voltage. When it is pulled up to the level and the voltage of Vpp high level is delivered to the node 56, the P14 transistor is turned off and the N35 transistor is turned on to pull the word line down to the VSS voltage level, while the P13 transistor is turned on and latched for a period of time. Disable WL0).
    When another word line is selected, if a low level voltage is transmitted to node 57 by turning on the N34 transistor among the N33 and N34 switch transistors connected to WLEN00B 53 and WLEN01B 52, the P17 transistor is turned on and the N36 transistor is turned on. It turns off to drive the word line WL1 of the word line Vpp level for a predetermined time. When the N34 transistor is turned off during the non-decoding, and the RPPO 51 becomes the low level voltage, the P15 transistor is operated to bring the node 57 to the VPP voltage. When it is pulled up to the level and the voltage of Vpp high level is delivered to the node 57, the P17 transistor is turned off and the N36 transistor is turned on to pull the word line to the VSS voltage level, while the P16 transistor is turned on and the word line is latched. Deactivate WLO).
    Hereinafter, respective configurations of the second to nth row decoders and word line drivers 100B to 100N are the same as those of the first row decoder and word line driver 100A, and Pxk (K = 0,1, The same operation is performed by 2,3, ..., n) signal.
    The redundant word line selector 200B inputs RWLENI and RWLENK, and when the normal operation is disabled, the redundant word line selection unit 200B is disabled in any of the RWLEN0 and RWLEN1 in the redundant state. Drive or deactivate RWL1, ...
    According to the word line driving circuit according to the present invention operating as described above, in order to select and drive one word line in a word line driving block having a plurality of word lines in the prior art, the entire decode must be operated accordingly. Although the current consumption is large, RDPR is provided by Pxk (k = 0, 1, 2, 3, ..., n) coding to provide a word line driving block having a plurality of word lines and to select and drive one word line. By dividing / WLEC through n control signals to drive the RDWLD block, current consumption can be reduced by nearly 1 / k and high speeds can be achieved.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] In a semiconductor memory device, N word lines connected to a plurality of memory cells having a matrix structure consisting of N rows and M columns are connected to a word line driver circuit for driving the corresponding word lines by a memory address signal generated from an upper controller side. The N word lines are divided into n word line groups, and one-to-one matching is connected to each of the divided n word line groups, and selected among the word lines belonging to the corresponding word line group. Determining which of the n word line groups belongs to the n word line group driving means for activating one and the memory address signal generated from the upper control part determines which of the n word line groups belongs to the n word line. Selecting one of the group driving means And a word line selection unit.
    [2" claim-type="Currently amended] In a semiconductor memory device, N word lines connected to a plurality of memory cells having a matrix structure of N rows and M columns are connected to a word line driving circuit for driving the corresponding word lines by a memory address signal generated from an upper controller side. And a row address-free which divides N word lines into n word line groups and receives an address from a row address buffer that stores a memory address signal generated by the upper controller. A bit line selection circuit that receives an address from the row address bumper and generates a signal for selecting a bit line corresponding to the address, and a driving control signal that is connected one-to-one to each of the n word line groups According to the above N row decoders and word line driver circuits and n bit line selection circuits for receiving a control signal of some of the control signals output from the low address predecoder and driving the n word line groups connected by the control signal; Determines a word line group corresponding to a memory address signal generated by the upper controller by receiving a signal output from a low address predecoder, and selects one of the n low decoders and the word line driving circuits accordingly, thereby selecting the corresponding low decoder. And a word line selector for inputting a drive control signal to the word line driver circuit.
    [3" claim-type="Currently amended] 3. The word line of claim 2, wherein a low-fuse unit that generates information on word lines that cannot receive an address from the row address buffer is provided, and the remaining word lines are divided into n word line groups. The word line driving circuit of the semiconductor memory further comprises an extra low decoder and a word line driving circuit.
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    同族专利:
    公开号 | 公开日
    JPH10199247A|1998-07-31|
    KR100231137B1|1999-11-15|
    US5889724A|1999-03-30|
    JP3194137B2|2001-07-30|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-28|Application filed by 문정환, 엘지반도체 주식회사
    1996-12-28|Priority to KR1019960075715A
    1998-09-25|Publication of KR19980056445A
    1999-11-15|Application granted
    1999-11-15|Publication of KR100231137B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960075715A|KR100231137B1|1996-12-28|1996-12-28|Word line driving circuit of memory device|
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